Transistor with means for providing a non-silicon-based emitter

ABSTRACT

A transistor includes a means for providing a non-silicon-based emitter with a flexible structure to relieve lattice mis-match between the emitter and the base.

CROSS REFERENCE TO RELATED APPLICATIONS

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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INCORPORATION BY REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC

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BACKGROUND

Many electronic devices, such as telecom devices, incorporatesemiconductors in their design and operation. Semiconductors can bedifferentiated from metals and insulators. The behavior of valence, orunbonded electrons in a given material helps to determine whether thatmaterial acts as a metal, an insulator, or a semiconductor. Electrons ina material occupy different quantum, or energy states, depending onfactors such as temperature and the absence or presence of an externallyapplied electrical potential. The highest energy quantum state occupiedby an electron for a given material, while that material is at 0°K isknown as the Fermi energy, E_(F).

In metals, the Fermi energy, E_(F) falls in the middle of a band ofallowed quantum states, closely spaced in energy. As a result, thismeans that an infinitesimally small voltage allows an electron to bepromoted from lower energy quantum states to higher energy quantumstates. Therefore, electrons may move freely through metals. The abilityto easily permit the movement of electrons in a material allows metalsto carry an electrical current. As such, metals are excellentconductors.

For insulators, the Fermi energy, E_(F) falls inbetween widely spacedquantum energy states. As a result, when compared to metals, acomparatively large voltage is required to promote an electron to a moreenergetic level. Electrons in insulators are much less mobile and cancarry far less current than metals in response to a given voltage.

Semiconductors are similar to insulators in that the Fermi energy, E_(F)falls inbetween spaced quantum energy states. However, the gap betweenthese energy states in a semiconductor is more narrow than the gap foran insulator. This allows electrons in semiconductors to be promoted byexternal energy from quantum states in the lower-energy valence bands toquantum states in the higher-energy valence bands. The ability ofelectrons in semiconductors to be promoted from one quantum state toanother provides the electron mobility needed for current flow.

Promotion of an electron produces a negatively charged mobile conductionband electron, or free electron, as well as a positively charged hole inthe valence band. Both the free electron and the hole are mobile chargecarriers that support the flow of current. The density of positive ornegative charge carriers in a semiconductor can be increased by addingionized impurities, or dopants, to a semiconductor. A semiconductormaterial with no added impurities is referred-to as an intrinsicsemiconductor. A semiconductor material with added dopants isreferred-to as an extrinsic semiconductor. An extrinsic semiconductorwith an increased density of positive charge carriers, or holes, isreferred-to as a p-type semiconductor. An extrinsic semiconductor withan increased density of negative charge carriers, or free electrons, isreferred-to as an n-type semiconductor.

Transistors and other semiconductor devices are based on junctionsbetween different semiconductor materials of different properties. Inheterojunctions, regions of different bulk semiconductor materials arejoined at an interface. For example, n-type semiconductors may beinterfaced with p-type semiconductors. In homojunctions, regions of thesame bulk semiconductor (all n-type, or all p-type), each with possiblydifferent levels or types of dopants to produce different semiconductorparameters, are joined at an interface.

At the interface, or junction between two semiconductor materials, adepletion region forms due to the movement of free electrons from then-type region into the adjoining p-type region, where the free electronscombine with the holes. This effectively collapses the free electronsand electron holes into bound valence electrons. These bound valenceelectrons in the depletion region result in a potential energy barrieragainst the migration of additional free electrons from the n-typematerial into the p-type material.

A forward bias may be applied to the semiconductor materials byconnecting a positive end of a voltage to the p-type material and thenegative end of the voltage to the n-type material. As the forward biasis increased, the depletion region narrows and eventually does notexist. At this point, as the voltage is further increased, current willbegin to flow between the semiconductor materials. When the forward biasis removed, or reduced to the point where the depletion region existsagain, current will not flow between the semiconductor materials.

Semiconductors are often incorporated in the construction ofmicrocircuit devices. A given microcircuit may have bipolar transistors,metal-oxide semiconductor (MOS) transistors, diodes, resistors, or anycombination thereof Bipolar transistors have at least threesemiconductor regions: A base of a first type of semiconductor material,and a collector and an emitter of a second type of semiconductormaterial. Microcircuits which incorporate bipolar transistors are oftenfabricated using silicon (Si) based materials and processes. MaximizingSi-based bipolar transistor performance is a goal of the Si integratedcircuit industry. In furtherance of this goal, the vertical dimensionsof bipolar transistors are being scaled back. The scaling-back mayresult in certain device operational limits. For example, when the basethickness is decreased, the doping level must be increased in order tocontrol the depletion region and maintain a low base resistance.Unfortunately, increasing the doping level of the base decreases thegain (and therefore the utility) of the bipolar transistor.

BRIEF SUMMARY

Not Applicable

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates one embodiment of a group III/VIsemiconductor heterojunction bipolar transistor (HBT).

FIGS. 2-4 illustrate sample performance of one embodiment of a groupIII/VI semiconductor HBT.

FIGS. 5A-5D illustrate embodiments of buried layer formation andisolation in an embodiment of a microcircuit device.

FIG. 6 illustrates embodiments of a group III/VI semiconductor HBT and ametal oxide semiconductor (MOS) transistor formed on the same embodimentof a microcircuit device.

FIG. 7 illustrates an embodiment of a process flow for the constructionof a BiMOS device having both a group III/VI semiconductor HBT and anMOS transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 schematically illustrates one embodiment of a layered groupIII/VI semiconductor heterojunction bipolar transistor (HBT). FIG. 1 isnot drawn to scale. The group III/VI semiconductor designation refers tosemiconductors made from combinations of elements from group III on theperiodic table and group VI on the periodic table. Examples of suitablecombinations for group III/VI semiconductors include GaS, GaSe, GaTe,InS, InSe, InTe, and TlS. For the sake of simplicity, InSe will be usedin the embodiment descriptions of layered group III/VI semiconductorHBT's.

The heterojunction bipolar transistor (HBT) 30, shown in the embodimentof FIG. 1, has a base 32 constructed of a p-type material coupled to abase contact 34, and coupled to an emitter 36 constructed of a layer ofgroup III/VI semiconductor, here shown as InSe. The InSe emitter 36 isan intrinsic n-type semiconductor, and may be used in this capacity, orthe InSe emitter 36 may be doped with n-type impurities to result in ann-type material with more free electrons than a substantially pure InSeemitter 36. The InSe emitter 36 is also coupled to an emitter contact38.

An n-type semiconductor layer 40 is coupled to the base 32. A buriedcollector 42, constructed from an enhanced n-type semiconductor layer,or an N⁺ type semiconductor, is coupled to a collector contact 44 andthe n-type semiconductor layer 40. Although it is preferable to have aburied collector 42, an HBT may be constructed without a buriedcollector 42. In this case, the n-type semiconductor layer 40 acts as acollector and would be coupled to the base 32 and the collector contact44. As illustrated in FIG. 1, this embodiment of a heterojunctionbipolar transistor (HBT) 30 is an n-type device, because the emitter isan n-type semiconductor, the base is a p-type semiconductor, and thecollector is an n-type semiconductor.

It is also possible to make a group III/VI emitter HBT 30 as a p-typedevice. To do this, the InSe emitter 36 must be doped with p-typeimpurities until it behaves as a p-type material. The base 32 would beconstructed of an n-type material. The n-type semiconductor layer 40would be replaced with a p-type semiconductor layer, and the buriedcollector 42 would be a replaced with an enhanced P⁺ type material.Although a p-type version of a group III/VI emitter HBT 30 is possible,an n-type version will be used throughout the specification for the sakeof explanation. This specification is intended, however, to cover bothn-type and p-type devices.

The base 32, the n-type semiconductor layer 40, and the buried conductor42 are preferably constructed of silicon (Si) based materials which havebeen doped with n-type or p-type impurities as described above. The InSeemitter 36 may be epitaxially grown on the Si-based base 32. Since InSecan have a wide energy band gap (1.4 electron volts (eV) to 1.9 eV orgreater) between allowable quantum energy states for valence electrons,as compared to the energy band gaps of 0.8 eV to 1.1 eV for priorSi-based emitters, the InSe emitter 36 and the base 32 may be madethinner while still maintaining a small depletion region between thebase 32 and the emitter 36 and without reducing the bipolar gain. Anepitaxially grown InSe emitter 36 also has the advantage of relativelylow-temperature requirements, low bulk and contact resistances, and goodstability during later interconnect process steps when compared to otherhigh band-gap materials such as GaP, semi-insulating poly-silicon films,oxygen-doped Si epitaxial films, —SiC, as well as phosphate dopedhydrogenated microcrystalline Si.

Table 1 shows simulation values for one embodiment of an HBT 30 havingan InSe emitter 36.

TABLE 1 Carrier Concentration Material Thickness Carrier Type(carriers/cm³) Emitter InSe  0.1 um N 1 × 10¹⁷ Base Si 0.05 um P 1 ×10¹⁸ Collector Si 0.95 um N 1 × 10¹⁵

FIG. 2 illustrates several collector current (I_(C))-collector voltage(V_(C)) curves 48 for the HBT 30 embodied in table 1. FIG. 3 illustratescollector current 50 (I_(C)) and base current 52 (I_(B)) as a functionof base voltage 54 (V_(B)) for the values embodied in table 1. A gain 56is also plotted to show the relative current gain from I_(B) 52 to I_(C)50 at a given V_(B) 54. FIG. 4 illustrates a cutoff frequency curve 58plotted as a function of I_(C). FIGS. 2-4 show that the HBT 30, asspecified by the parameters in table 1, has a reasonable gain andfrequency response. HBT 30 performance can be altered to meet aparticular gain and frequency response criteria by altering thethickness of the base, changing the doping level of the base, and/orchanging the doping level of the emitter. Such alterations arewell-within the abilities of those skilled in the art, and the valuesillustrated in table 1 are not intended to be limiting in any way.

At an atomic lattice level, The InSe emitter 36 is a layeredsemiconductor compound. The layers interact with each other throughVanderwaal forces, while within the layer, atoms are bound by valenceforces. The Vanderwaal forces are less than the valence forces, allowingflex between layers. This flexibility of the InSe emitter 36 acts as abuffer between the mismatched lattice structure of the Si base 32 andthe emitter 36. Other non-silicon, and non-group III/VI emitters havelattice structures which are difficult to grow on a silicon substrate,but the flexibility of the layered group III/VI emitter 36 is lesssusceptible to manufacturing issues. Multiple HBT's 30 may be formed ona single integrated circuit, microchip, or microcircuit, and the InSeemitter 36 can be successfully manufactured through epitaxial growth ata temperature below 500° C. This relatively low thermal budget shouldmake the group III/VI high band-gap emitter HBT 30 attractive to theintegrated circuit industry, since such HBT's 30, with advantagespreviously noted, can be formed in concert with MOS (metal oxidesemiconductor) processes. Micro-circuits with both bipolar transistorsand MOS transistors are known as BiMOS devices. BiMOS devices areespecially useful in applications which need the Bipolar transistors foranalog signal conditioning and the MOS transistors for digital signalconditioning and processing.

FIGS. 5A-6 illustrate an embodiment of the construction of a BiMOSdevice, or microcircuit 59, having at least one group III/VI emitter HBT30. For simplicity of illustration, InSe will be used as an example of agroup III/VI emitter, but other group III/VI combinations arc possible,as previously discussed.

The starting point in this embodiment of a microcircuit 59 is the buriedlayer formation. FIG. 5A illustrates in side cross-section a slice ofsemiconductor grade Si which has either been diffused with n-typeimpurities, epitaxially grown from a seed layer of Si to include then-type impurities, or ion-implanted with n-type impurities to form ann-type buried semiconductor layer 60. The n-type buried layer 60 has afirst side 62 and a second side 64. A protective layer 66 of SiO₂ maythen be formed on the first side 62 of the n-type buried layer 60.

Throughout the steps described in FIGS. 5A-6, certain actions mayrequire the selective coating, epitaxial growth, etching, insulating,diffusion, or ion implantation of some regions on the microcircuit,while others are left alone. This selective processing may beaccomplished through the use of masking techniques which are well-knownto those skilled in the art. Such masking techniques may include, forexample, photolithographic films, use of photoresist, and conductivefilms. Although such masking techniques may be integral to theproduction process wherever selective deposition, diffusion, growth,insulating, etching, or sealing occurs, they are not described for eachstep for the sake of simplicity of explanation, and since it is withinthe abilities of one of ordinary skill in the art to choose to use oneor more of several masking techniques based on the desired application.

As FIG. 5B illustrates, trenches 68 may be etched through the protectivelayer 66 and into the n-type buried layer 60. As FIG. 5C illustrates,the trenches 68 are oxidized to form a new protective SiO₂ layer 70.This creates a new first side 72 opposite the second side 64. Apolycrystalline Si support layer 74 may be formed on the first side 72against the protective layer 70, filling the trenches 68. Thepolycrystalline Si support layer 74 gives strength to the microcircuitdevice 59. Addition of the support layer 74 results in a new first side76 opposite the existing second side 64. A cut-line 78 is shown in FIG.5C. The microcircuit device 59 is then flipped over so that the firstside 76 is facing downward as shown in FIG. 5D. Through a cutting,grinding, etching, or polishing process, the microcircuit 59 is cutalong cut-line 78. As shown in FIG. 5D, this creates electricallyisolated pockets 80 of n-type buried layer 60, which are isolated by theinsulating protective SiO₂ layer 70. The described isolation processshown in FIGS. 5B-5D may also be used in conjunction with a wellformation step, whereby areas of p-type impurities are introduced intothe n-type buried layer 60 to create areas in which n-type MOStransistors or p-n-p type bi-polar transistors may be constructed.P-type MOS transistors and n-p-n type bi-polar transistors may be formedin the illustrated n-type buried layer 60, and for the sake ofsimplicity, this embodiment will not include well-formation. It shouldbe understood, however, that well-formation is compatible with theembodiments of this specification and their equivalents.

The remaining actions in the construction of the microcircuit device 59are discussed with reference to FIG. 6. FIG. 6 is an enlarged sidecross-sectional view showing two isolated pockets 80A and 80B. Aheterojunction bipolar transistor (HBT) is formed in pocket 80A, and aMOS transistor is formed in pocket 80B. A deep N+ collector 82 is formedthrough diffusion or ion implantation. The N+ collector 82 has moren-type impurities than the n-type buried layer 60.

A gate oxide 84 is formed by selectively exposing the microcircuitdevice 59 to appropriate temperature and atmospheric conditions to forma layer of SiO₂ on the pocket 80B where it is desired to have the MOSgate. Appropriate oxidation techniques are well-known to those skilledin the art. A poly-Si layer 86 is formed on-top of the gate oxide 84 byepitaxy. Next, the HBT base 88 is formed in the buried layer 60 ofpocket 80A by diffusing or ion implanting p-type impurities into theburied layer 60. An insulating layer 90, here made of SiO₂ is formedon-top of the pockets 80A and 80B, leaving openings for contact to thesemiconductor material as necessary.

The relatively high-temperature process of P+ source and drain formationoccurs next, at temperatures of approximately 900° C. Source 92 anddrain 94 are formed in the buried layer 60 of pocket 80B. A P+semiconductor has more p-type impurities than a standard p-typesemiconductor. Oxides 96, 97 may be formed respectively over the exposedareas of the source 92 and the drain 94.

The next action is formation of the HBT emitter 98. Emitter 98 is formedof a group III/VI material, here InSe. InSe is a layered semiconductorcompound which can be grown with a large bandgap in the range of 1.4 eVto 1.9 eV or higher. As previously mentioned, the InSe emitter 98 haslayers which interact with each other through Vanderwaal forces, whilewithin the layers, atoms are bound by valence forces. This layeredemitter 98 serves as a buffer to release strains caused by latticemis-match between the base 88 and the emitter 98. InSe can beepitaxially grown at temperatures below 50020 C. on Si as a bipolaremitter 98. This makes group III/VI emitters, such as InSe emitter 98,attractive to the silicon integrated circuit industry, since the highband gap and relatively low temperature requirements allow smallervertical dimension HBT devices to be formed on a BiMOS microcircuitdevice 59, after the standard MOS processes, with a minimal thermalbudget impact.

The final actions involve the formation of contacts for electricalcontinuity with other semiconductor devices on the same microcircuit 59,or with interconnects to the outside world. A base contact 100 is formedin the gap in the protective layer 90 over the base 88. An emittercontact 102 is formed on the InSe emitter 98. A collector contact 104 isformed in the gap in the protective layer 90 over the collector 82. Asource contact 106 is formed over the source oxide 96, a drain contact108 is formed over the drain oxide 97, and a gate contact 110 is formedover the poly-Si gate interface 86.

FIG. 7 illustrates an embodiment of actions which may be used toconstruct a BiMOS device (a device having both bipolar and MOS typetransistors on the same microcircuit), such as microcircuit device 59.Masking steps are omitted, and may be implemented as necessary by thoseskilled in the art. The construction or manufacturing begins with buriedlayer formation 112. Isolation 114 of the buried layer into separateregions occurs next. The HBT collectors are created by deep N+ formation116. MOS gate oxides are formed 118, and a poly-Si layer is formed 120on each MOS gate oxide. The HBT bases are formed 122 through theappropriate diffusion or ion implantation of impurities in the buriedlayer. Source and drain areas of the MOS regions are formed 124 throughdiffusion or ion implantation. A group III/VI semiconductor isepitaxially grown to form an emitter 126 on the HBT base. Finally,contact formation 128 is performed to link semiconductor devicestogether and/or to provide interconnect to the microcircuit.

Although InSe was primarily used as an example of an appropriate groupIII/VI semiconductor, it is apparent that other group III/VIsemiconductors may be used and are deemed to be within the scope of theclaims below. The embodiments discussed herein have described an n-typeHBT with a group III/VI emitter. A p-type HBT is also possible by usingan n-type base, a p-type collector, and doping the InSe emitter withp-type impurities. The described manufacturing embodiments areillustrative of the construction of an HBT with a group III/VI emitteror of the construction of a BiMOS device having at least one HBT with agroup III/VI emitter. Other methods of isolation may be used, such asjunction isolation, and other steps, such as well-formation or LDDformation (to optimize the collector performance) may be included asdesired. Other semiconductor devices, such as diodes and n-type MOStransistors may be formed on a BiMOS microcircuit in addition to then-type HBT and p-type MOS transistor as illustrated in the embodiments.The relatively low thermal budget of the group III/VI emitter providesexcellent compatibility with MOS processes, and the order ofconstruction steps may be varied where possible while still stayingbelow the thermal budget of the group III/VI layer once it has beenformed. Additionally, it is apparent that a variety of otherstructurally and functionally equivalent modifications and substitutionsmay be made to implement an embodiment of a group III/VI emitter HBT ora BiMOS device including an HBT with a group III/VI emitter according tothe concepts covered herein, depending upon the particularimplementation, while still falling within the scope of the claimsbelow.

1. A transistor, comprising: a base; a collector; an emitter comprisinga group III/VI semiconductor; and an emitter contact coupled to theemitter.
 2. The transistor of claim 1, wherein: the base comprises ap-type semiconductor material; and the collector comprises an n-typesemiconductor material.
 3. The transistor of claim 1, wherein: the groupIII/VI semiconductor is doped to behave as a p-type semiconductor; thebase comprises an n-type semiconductor; and the collector comprises ap-type semiconductor.
 4. The transistor of claim 1, wherein thecollector comprises a buried collector.
 5. The transistor of claim 1,wherein the emitter further comprises an n-type dopant.
 6. Amicrocircuit, comprising: at least one metal oxide semiconductor (MOS)transistor; and the transistor of claim
 1. 7. A transistor, comprising:a base; a collector; and an emitter comprising a group III/VIsemiconductor, wherein the group III/VI semiconductor is selected fromthe group consisting of GaS, GaSe, GaTe, InS, InSe, InTe, and TIS.
 8. Atransistor, comprising: a base made of a silicon material; a collector;and means for providing a non-silicon-based emitter with a flexiblestructure to relieve lattice mis-match between the emitter and the base,the emitter comprising a group III/VI semiconductor.
 9. A transistor,comprising: a base constructed of a p-type silicon material; a basecontact coupled to the base; an emitter constructed of a group III/VIsemiconductor, including InSe, comprising an n-type semiconductor; anemitter contact coupled to the emitter; an n-type semiconductor layercoupled to the base; a collector contact; and a buried collectorconstructed from an enhanced n-type semiconductor layer, coupled to thecollector contact and the n-type semiconductor layer.